TLK3104SA_09 Datasheet, PDF (29/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
PARALLEL SIDE DATA PINS (CONTINUED)
RDC(0−7)
R14, R15, R16,
R17, P13, P15,
P16, N13
1.8V HSTL/
SSTL_2 Output
RDD(0−7)
R11, T11, N12, P12, 1.8V HSTL/
R12, R13, T13, U13 SSTL_2 Output
RDB8
RDC8
RDD8
E15, N15, T14
1.8V HSTL/
SSTL_2 Output
Receive data pins, channels B−D, When PSYNC=low, parallel data on these buses is
valid on the rising and falling edge of the recovered data clock (RCB, RCC, or RCD).
When PSYNC=high, data on each bus is valid on the rising and falling edge of RCA.
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lvinaelid. on the rising and falling edge of the recovered data clock (RCB, RCC, or RCD).
When PSYNC=high, data on each bus is valid on the rising and falling edge of RCA.
These pins are series terminated to provide direct connection to a 50-Ω transmission
Receive data/K-flag, channels B−D When PSYNC=low, data on this pin is valid on the
rising and falling edge of the recovered clock (RCB, RCC, or RCD). When
PSYNC=high, data on this pin is valid on the rising and falling edge of RCA.
When CODE = low, these pins is the 9th bit of a received 8-B/10-B encoded byte.
When CODE = high, these pins act as the K- character flag. When asserted high, this
indicates the data on RDx(0−7) is a valid K-character.
These pins are series terminated to provide direct connection to a 50-Ω transmission
line.
RDB9
RDC9
RDD9
E16, N16, U14
1.8V HSTL/
SSTL_2 Output
Receive data pin/error detect, channels B−D. When PSYNC=low, data on these pins
are valid on the rising and falling edge of recovered channel clock (RCB, RCC, RCD).
When PSYNC=high, data on these pins are valid on the rising and falling edge of RCA.
When CODE = low, these pins are the 10th bit of a 8-B/10-B encoded byte. When
CODE = high, these pins provide an error detection flag. The error detect is asserted
high to signify the occurrence of either a disparity error or an invalid code word during
the decoding of the received data.
These pins have internal series termination to provide direct connection to a 50-Ω
transmission line.
TDA(0−7)
TDA8
C8, B8, A8, E9, D9, 1.8V HSTL/
C9, E10, D10
SSTL_2 Input
C10
1.8V HSTL/
SSTL_2 Input
Transmit data pins, channel A, Parallel data on this bus is clocked on the rising and
falling edge of TCA.
Transmit Data/KGEN, channel A When CODE = low, this pin is the 9th bit of a 8-B/10-B
encoded byte to be transmitted. When CODE = high, this pin acts as the K-character
generator indicator. When high, this pin causes the data on TDA(0−7) to be encoded
into a K-character.
TDA9
TDB(0−7)
TDC(0−7)
TDD(0−7)
B10
1.8V HSTL/
SSTL_2 Input
F13, F14, F15, G13,
G15, G16, H13,
H15
M13, M14, M15,
L13, L15, L16, K13,
K15
R8, T8, U8, N9, P9,
R9, N10, P10
1.8V HSTL/
SSTL_2 Input
Transmit data pin, channel A, When CODE = low, this pin is the 10th bit of a 8-B/10-B
encoded byte. When CODE = high, this pin is ignored.
Transmit data pins, channels B−D, When PSYNC=low, parallel data on this bus is
clocked on the rising and falling edge of the transmit channel clock (TCB, TCC, TCD).
When PSYNC=high, data on these buses is clocked on the rising and falling edge of
TCA.
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