TLK3104SA_09 Datasheet, PDF (6/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
block diagram
Following is a more detailed block diagram description of each channel core.
LPENx
PRBSEN
CODE
TCx
TDx(0−9) Tx FIFO
TDx(0−7)
8-B/10-B
Encoder
KGENx
TDx(0−9)
PRBS
Generator
10
MUX ¹⁰
Parallel to
Serial
10
10
MUX
Baud Clock
TXxP
TXxN
RFCN
RFCP
RCx
RCA
PSYNC
MUX
Multiplying Clock
Synthesizer
Baud Clock
Interpolator and
Clock Recovery
Recovered
Clock
RDx(0−7) ^{PRBS Verification/}
8-B/10-B Decoder
10
RDx(0−9) MUX
KFLAGx
10
Serial to
10
Parallel and
Comma Detect
MUX
RXxP
RXxN
CODE
detailed description
The TLK3104SA has four operational interface modes controlled by the state of pins CODE and PSYNC. These
operational interface modes are listed in Table 1.
Table 1. Operational Modes
CODE PSYNC
DESCRIPTION
Low
Low Four independent serializer/deserializers (SERDES)
Low
High Four synchronized serializer/deserializers (SERDES)
High
Low Four independent transceivers with on-chip 8-B/10-B encode/decode
High
High 10 Gigabit ethernet XGXS† transceiver
† _{XGXS: XGMII extended sublayer}
serdes modes
When CODE is low, the TLK3104SA performs serialization and deserialization of encoded data across four ten
bit interfaces (TBI) similar to that done in fibre channel and 802.3z gigabit ethernet SERDES devices. The
channels can be synchronized to allow use of one transmit data clock and one receive data clock.
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