TLK3104SA_09 Datasheet, PDF (17/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
high-speed VML output
The high-speed data output driver is implemented using voltage mode logic that offers PECL-compatible
differential pair for a 100-Ω differential impedance environment with no external components. The line can be
directly coupled or ac-coupled. Refer to Figure 24 and Figure 25 for termination details.
Both current mode logic (CML) and PECL drivers require external components to provide a rising edge (CML)
or a falling edge (PECL). The disadvantage of the external edge control is a limited edge rate due to package
and line parasitics. In contrast, VML drivers drive and control both the rising and falling edge inside the package
and therefore provide optimum performance for increased speed requirements. Furthermore, the VML driver
controls the output voltage swing and adjusts automatically for varying load conditions. The PECL-compatible
output provides a nominal 850 mV (singled-ended) swing centered at V_DDA/2. The receiver input is internally
biased to facilitate ac-coupling. The receiver internal circuitry sets the common mode voltage to 2×V/_DDA/3.
When transmitting data across long lengths of PCB trace or cable, the high frequency content of the signal is
attenuated due to the skin effect of the media. This causes a smearing of the data eye when viewed on an
oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to
provide equalization for the high frequency loss, the differential swing is increased or preemphasized for the
bit immediately following a transition and subsequently reduced or de-emphasized for run lengths greater than
one, as shown in Figure 14. This provides additional high frequency energy to compensate for PCB or cable
loss. The level of the preemphasis is programmable via MDIO register bits 16-20.4:5. Users can control the
strength of the preemphasis to optimize for a specific system requirement. There are two control bits in the user
defined registers of MDIO to set the preemphasis level, as shown in Table 7. Refer to Table 15 for MDIO settings.
Table 7. Programmable Preemphasis
PRE1
(reg.16−20.4)
1
PRE2
(reg. 16−20.5)
1
PREEMPHASIS LEVEL
(VOD(p)/VOD(d)−1)†
Preemphasis disabled
0
1
10%
1
0
20%
0
0
30%
† _{VOD(p): Magnitude of the voltage swing when there is a transition in the data stream}
VOD(d): Magnitude of the voltage swing when there is no transition in the data stream
VCMT
Vod(p)
Vod(d)
Vod(p)
Vod(pp)
Vod(pd)
Vod(d)
Bit
Time
Bit
Time
Figure 14. Output Differential Voltage Under Preemphasis
device configuration
The TLK3104SA has three operational configurations controlled by two configuration pins CONFIG0 and
CONFIG1. These configurations are listed in Table 8 and controlled by the MDIO interface (refer to Table 15).
When the device is put in a certain mode, unused circuit blocks are powered down to conserve the system
power.
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