TLK3104SA_09 Datasheet, PDF (25/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
Table 19. Channel D Configuration Registers Bit Definitions (Register 20)
BIT(s) NAME
DESCRIPTION
READ/WRITE
20.15:11 Reserved
Read returns, write is ignored.
Read only
20.10:9 Multifunction pin output
Multifunction (MFD) pin configuration for channel D
20.10 20.9 MFD output
00
HSTL=1, SSTL_2 = 0 (default)
01
1 = Comma detected, 0 = data.
10
Register bit 22:3 (LOS)
11
Register bit 22:7 (PRBS Pass)
Logically ORed with register bit 16.10:9
Read/Write
20.8 Loss of signal detection 1 = Enable loss of signal condition described in Table 5 for channel D (default).
0 = Disable this function.
Logically ANDed with register bit 16.8
Read/Write
20.7 Configuration: CONFIG1 Configuration bits (see Table 8), default value = 0
When CONFIG1 = low, this bit can be set to 1.
When CONFIG1 = high, this bit read only.
Logically ORed with external input CONFIG1
and register bit 16.7
Read/Write
20.6 Configuration: CONFIG0 Configuration bits (see Table 8), default value = 0
When CONFIG0 = low, this bit can be set to 1.
When CONFIG0 = high, this bit read only.
Logically ORed with external input CONFIG0 and register bit 16.6
Read/Write
20.5 Preemphasis: PRE2
Programmable preemphasis control (see Table 7), default value = 0
Logically ORed with register bit 16.5
Read/Write
20.4 Preemphasis: PRE1
Programmable preemphasis control (see Table 7), default value = 0
Logically ORed with register bit 16.4
Read/Write
20.3 Loopback
1 = Enable loopback mode on channel D.
0 = Disable loopback mode on channel D (default).
Logically ORed with register bit 0.14
Read/Write
20.2 PRBS enable
1 = Enable pseudo-random bit stream internal generation and verification on channel D
0 = Normal operation (default).
Logically ORed with register bit 16.2
When PRBSEN = low, this bit can be set to 1.
When PRBSEN = high, this bit is read only.
Read/Write
20.1 Comma detect enable
1 = Enable K28.5 code detection and bit alignment on channel D (default).
0 = Disable K28.5 code detection on channel D.
Logically ANDed with SYNCEN and register bit 16.1
Read/Write
20.0 Power down
1 = Power down mode is enabled for channel D.
0 = Normal operation (default).
Logically ORed with register bit 0.11
Read/Write
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
25