TLK3104SA_09 Datasheet, PDF (16/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
receive synchronization and skew compensation (continued)
When the TLK3104SA is configured in independent channel mode, the recovered clocks for each channel are
used to output the received data on the parallel interface. Thus, as is shown in Figure 13, in the independent
channel modes, no FIFO is enabled.
Protocol Device
TLK3104
Channel
Logic
Channel A
RCA
Data A
RCLKA
Serdes
Core
Channel
Logic
Channel B
RCB
Data B
RCLKB
Serdes
Core
Channel
Logic
Channel C
RCC
Data C
RCLKC
Serdes
Core
Channel
Logic
Channel D
RCD
Data D
RCLKD
Serdes
Core
Xtal OSC ^RFCP/RFCN
Figure 13. Receive and Reference Clock Relationship (Independent Channel Modes)
parallel to serial
The parallel-to-serial shift register on each channel takes in 10-bit wide data from either the 8-b/10-b encoders,
if enabled, or directly from the transmit data bus and converts it to a serial stream. The shift register is clocked
by the internally-generated bit clock, which is 10 times the reference clock (RFCP/RFCN) frequency. The least
significant bit (LSB) for each channel is transmitted first.
serial to parallel
For each channel, serial data is received on the RXxP/RXxN pins. The interpolator and clock recovery circuit
locks to the data stream if the clock to be recovered is within ±100 PPM of the internally generated bit rate clock.
The recovered clock is used to retime the input data stream. The serial data is then clocked into the
serial-to-parallel shift registers. If enabled, the 10-bit wide parallel data is then fed into 8-b/10-b decoders. If the
TLK3104SA is configured in one of the synchronized channel modes, the parallel data for each channel is fed
into a FIFO buffer where the output is synchronized to RCA. If the TLK3104SA is configured in one of the
independent channel modes, the parallel data for each channel is output synchronized to each channel’s
recovered clock.
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