TLK3104SA_09 Datasheet, PDF (39/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

50 Ω
Output
TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
VREF
50 Ω
50 Ω
(optional)
+
Transmission Line
VDDQ
_
RΩ
PCB
RΩ
GND
Vref
Input
NOTE: The output buffer of the TLK3104SA has on-chip termination of 50 Ω. The
output signal is compliant with the JEDEC SSTL_2 Class 1 specification.
Line termination on the receive end is optional and not recommended for
low-power applications.
Figure 26. SSTL_2 Class 1 I/O
50 Ω
Output
50 Ω
Transmission Line
PCB
+
VDDQ
_
RΩ
RΩ
GND
Vref
Input
NOTE: The TLK3104SA provides a push-pull effect on the output buffer for
externally sourced series terminated loads. In HSTL mode, the signal swing
is very small, allowing for minimal power consumption and low
electromagnetic emission (EME). To assure sufficient signal levels on the
receive side, no termination resistor is used.
Figure 27. 1.8V HSTL I/O
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