TLK3104SA_09 Datasheet, PDF (19/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

MDIO management interface (continued)
MDC
TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
MDIO
32 “1”s
0
1
0
1
A4
A0
R4
R0
1 0 D15 D0
Preamble
SFD
PHY Address
Data
Idle
Register Address
Write Code
Turn Around
Figure 16. Management Interface Write Timing
The MDIO Interface allows up to 32 (16-bit) internal registers. Sixteen registers are defined by the IEEE 802.3
clause 22 specification. Additional registers are allowed for expanded functionality. The TLK3104SA
implements five IEEE defined registers. The TLK3104SA also implements seven registers for expanded
functionality. Both the IEEE defined registers and the expanded functionality registers are outlined in Table 9.
REGISTER ADDRESS
0
1
2,3
4-14
15
16
17:20
21
22
23
Table 9. MDIO Registers
REGISTER NAME
Control
Status
PHY identifier
Not applicable
Extended status
Global configuration
Channel A-D configuration
Reserved
Channel status
Channel sync status
DEFINITION
IEEE 802.3 Defined. See Table 10
IEEE 802.3 Defined. See Table 12
IEEE 802.3 Defined. See Tables 12 and 13
IEEE 802.3 Defined. See Table 14
See Table 15
See Tables 16 through 19
Reserved
See Table 20
See Table 21
Table 10. Control Register Bit Definitions (Register 0)
BIT(s)
NAME
DESCRIPTION
0.15 Reset
Logically ORed with the inverse of RSTN pin.
1= Global resets including FIFO clear
0= Normal operation
0.14 Loopback
1=Enable loopback mode on all channels.
0=Disable loopback mode on all channels (default).
0.13 Speed selection (LSB)
Not applicable. Read returns a 1.
0.12 Auto-negotiation enable
Not applicable. Read returns a 0.
0.11 Power down
Logically ORed with the inversion of the ENABLE pin.
1 = Power down mode is enabled.
0 = Normal operation (default).
0.10 Isolate
Not applicable. Read returns a 0.
0.9 Restart auto-negotiation
Not applicable. Read returns a 0.
0.8 Duplex mode
Only full duplex is supported. Write is ignored, read returns a 1.
0.7 Collision test
Not applicable. Read returns a 0.
0.6 Speed selection (MSB)
Not applicable. Read returns a 1.
0.5:0 Reserved
Write as 0. Ignore on read
† _{After reset bit is set to one, it automatically sets itself back to zero on the next MDC clock cycle.}
‡ _{Writing to this bit position is ignored.}
READ/WRITE
Read/Write
Self Clearing†
Read/Write
Read only‡
Read only†
Read/Write
Read only†
Read only†
Read only†
Read only†
Read only†
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