TLK3104SA_09 Datasheet, PDF (10/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
channel clock to serial transmit clock synchronization (continued)
Protocol Device
TLK3104SA
Channel
Logic
Channel A
TCA
TX
FIFO
Data A
Channel
Logic
Channel B
TCB
TX
FIFO
Data B
Channel
Logic
Channel C
TCC
TX
FIFO
Data C
Channel
Logic
Channel D
TCD
TX
FIFO
Data D
Serdes
Core
Serdes
Core
Serdes
Core
Serdes
Core
RFCP/RFCN
Xtal OSC
Figure 7. Transmit and Reference Clock Relationship (Independent Channel Mode)
receive data bus timing
For each channel, the receiver portion of the TLK3104SA outputs the recovered deserialized data on receive
data bus TDx[0..9] on both the rising and falling edges of the receive data clock, as shown in Figure 8. Depending
on the state of PSYNC pin the receive data clock is either RCA (channel sync mode) or the individual receive
channel clocks, RCA−RCD (independent channel mode). When in the channel sync mode, RCB, RCC, and
RCD pins are held low.
RCA, RCB,
RCC, RCD
RDx[0...9]
th
tsu
Data
tsu
th
Data
Figure 8. Receive Interface Timing
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