TLK3104SA_09 Datasheet, PDF (31/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
Terminal Functions (Continued)
TERMINAL
NAME NO.
JTAG TEST PORT INTERFACE
TYPE
TCLK
A3
LVTTL Input
TDI
B3
LVTTL Input†
TDO
A2
LVTTL Output
TMS
B2
LVTTL Input†
TRSTN
A1
LVTTL Input
MANAGEMENT DATA INTERFACE
R1, T1, T3,
DVAD(0−4) _{T2, R2}
LVTTL Input
MDC
U2
LVTTL Input
MDIO
U3
MISCELLANEOUS PINS
CODE
P1
LVTTL I/O
LVTTL Input†
DESCRIPTION
JTAG clock. TCLK is used to clock state information and test data into and out of the device
during the operation of the test port.
JTAG input data. TDI is used to serially shift test data and test instructions into the device
during the operation of the test port.
JTAG output data. TDO is used to serially shift test data and test instructions out of the device
during operation of the test port. When the JTAG port is not in use, TDO is in a high
impedance state.
JTAG mode select. TMS is used to control the state of the internal test-port controller.
JTAG reset. TRSTN is used to reset the internal JTAG controller.
Management address. Device address: DVAD(0-4) is the externally set physical address
given to this device used to distinguish one device from another.
Management data clock. MDC is the clock reference for the transfer of management data to
and from the protocol device.
Management data I/O. MDIO is the bidirectional serial data path for the transfer of
management data to and from the protocol device.
Encode enable. When CODE = high, the 8-B/10-B encoder and decoder is enabled.
CONFIG0
CONFIG1
C2, D2
ENABLE
U1
LPEN(A−D) C3, D3, P3,
R3
MF(A−D)
A16, B16,
T16, U16
PRBSEN
J1
PSYNC
C1
RSTN
B1
SYNCEN D1
TESTEN
P2
† _{With 10 kΩ internal pullup}
‡ _{With 10 kΩ internal pulldown}
LVTTL Input‡
LVTTL Input†
LVTTL Input‡
1.8V HSTL_/
SSTL_2 Output
LVTTL Input‡
LVTTL Input‡
LVTTL Input†
LVTTL Input†
LVTTL Input‡
Configuration pins. These pins put the device under one of the three operation modes:
00−Transceiver mode
01−Transmit only mode
10−Receive only mode
11 – Reserved
Standby enable. When this pin is held low, the device is in a low power state. When high the
device operates normally.
Internal loop enable. channels A−D. When high, the serial output for each channel is
internally looped back to its serial input.
Multifunction outputs, channels A−D. The functions of these pins are enabled via the MDIO.
Currently defined functions are:
1. Pin indicates 1 for HSTL, 0 for SSTL_2 Signaling (default)
2. LOS (Loss of Signal) for each channel,
3. COMMA_DET (K28.5 character detected) for each channel, and
4. PRBS_STATUS (pseudo-random bit stream test status) for each channel.
PRBS enable. When this pin is asserted high, the pseudo-random bit stream generator and
comparator circuits are inserted into the transmit and receive data paths on all channels.
PRBS_PASS is indicated on the MFx pins once they are enabled using MDIO.
Channel synchronization enable. When PSYNC = high, all transmit data is latched on the
rising and falling edge of TCA, all receive data is valid on the rising and falling edge of RCA.
Chip reset (FIFO clear). Pulling this pin low re-centers the transmit skew buffers, receive
channel synchronization FIFO’s, and resets MDIO flags.
Comma detect enable. When high, comma detection and byte alignment for all channels is
enabled.
Test mode enable. This pin is used for manufacturing test. This pin should be left
unconnected or tied low.
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