TLK3104SA_09 Datasheet, PDF (3/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

system block diagram
TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
TCA..D
RCA..D
MAC/
Switch
Fabric
TDA..D(0:9) _TX+
TX−
XGMII
TLK3104SA
XGXS
RCA..D
RDA..D(0:9) ^RX+
RX−
4
4
XAUI
4
4
RX+RDA..D(0:9)
RX−
TLK3104SA
XGXS
XGMII
TCA..D
TX+ TDA..D(0:9)
TX−
PCS
Clk
16:1
TX MUX
E/O
16
Clk
1:16
CDR/
O/E
16 ^Deserializer
MDIO MDC
MDIO MDC
MDIO MDC
6”
20”
6”
3”
Management
Figure 1. System Block Diagram (Chip-to-Chip Implementation)
Figure 2 shows an example system block diagram for TLK3104SA used to provide the 10 Gbps ethernet
physical coding sublayer (as defined in IEEE802.3ae Clause 48) to coarse wave-length division multiplexed
(CWDM) optical transceiver
4
4
Backplane
TLK3104SA
4
4
TCA..D
MAC/
Packet
Processor
TDA..D(0:9) _TX+
TX−
TLK3104SA
XGMII
PCS
4
4
XAUI
RCA..D
RDA..D(0:9) ^{RX+ 4}
RX−
4
CWDM
Optics
Figure 2. System Block Diagram (PCS Implementation)
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