TLK3104SA_09 Datasheet, PDF (33/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
absolute maximum ratings over operating free-air temperature (unless otherwise noted)^†
Supply voltage, V_DD , V_(DDQ) , V_(DDA) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 3 V
Input voltage: V_I (LVTTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4 V
1.8V HSTL/ SSTL_2 CLASS 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 4 V
DC input voltage (I/O) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 3 V
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HBM: 2KV, CDM:750V
Characterized free-air operating temperature range (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are stated with respect to network ground terminal.
2. To achieve 70°C ambient temperature requires 1 m/s air flow.
recommended operating conditions
MIN NOM MAX UNIT
Core supply voltage, VDD
I/O supply voltage, V(DDQ)
SSTL_2 Class 1
1.8 V HSTL Class 1
2.3 2.5 2.7 V
2.3 2.5 2.7
V
1.7 1.8 1.9
Analog supply voltage, V(DDA)
Core supply current, IDD
I/O supply current, I(DDQ)
Analog supply current, I(DDA)
Total power consumption, (SSTL), PD
Total power consumption, (HSTL), PD
Input reference voltage‡, V(REF)
fI = 156.25 MHz
SSTL_2 Class 1,
1.8V HSTL Class 1,
fI = 156.25 MHz
Transceiver mode,
Transmit mode,
Receive mode,
Transceiver mode,
Transmit mode,
Receive mode,
SSTL_2 Class 1
1.8V HSTL Class 1
fI = 156.25 MHz
fI = 156.25 MHz
fI = 156.25 MHz
fI = 156.25 MHz
fI = 156.25 MHz
fI = 156.25 MHz
fI = 156.25 MHz
fI = 156.25 MHz
2.3 2.5 2.7 V
400 540 mA
160 270
mA
125 195
300 350 mA
2.2 3.1 W
1.3 1.6 W
2.2 2.9 W
2.1 2.7 W
1.3 1.42 W
1.8 2.2 W
1.15 1.25 1.35 V
0.85 0.90 0.95 V
Analog shutdown current, I(SDA)
Core shutdown current, I(SDD)
Enable = low
Enable = low
60
µA
1
mA
Core shutdown current, I(SDQ)
Enable = low
5
µA
‡ _{The value of V(REF) may be selected to provide optimum noise margin in the system. Typically the value of VREF is expected to be 0.4 × V(DDQ)}
of the transmitting device, and V(REF) is expected to track variations in V(DDQ). Peak-to-peak ac noise on V(REF) may not exceed +2% V(REF)(dc).
reference clock timing requirements (RFCP/N) over recommended operating conditions (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
fI
Frequency
Minimum data rate
Maximum data rate
TYP−0.01% 125 TYP+0.01%
MHz
TYP−0.01% 156.25 TYP+0.01%
Accuracy
−100
100 ppm
Duty cycle
40% 50%
60%
Jitter
Random and deterministic
40 ps
NOTE: This clock should be crystal referenced to meet the requirements of the above table. Contact TI for specific clocking recommendations.
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