TLK3104SA_09 Datasheet, PDF (18/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
device configuration (continued)
Table 8. Device Configurations
CONFIG0
Low
Low
High
High
CONFIG1
Low
High
Low
High
CONFIGURATION
Full duplex transceiver mode—normal operation (default after reset).
Transmit only mode—data on high-speed data inputs is ignored. Receive data bus is in a high-impedance state.
Receive only mode—high speed data outputs are in a high impedance state. Data on the transmit data bus is ignored.
Reserved
PRBS generator
The TLK3104SA has a built-in 2⁷-1 pseudo-random bit stream (PRBS) self-test function available on each
channel. Compared to all 8-B/10-B data pattern combinations, the PRBS is worst case bit pattern. Therefore it is
very sufficient to test the link and jitter tolerance. The self test function is a enabled using the PRBSEN pin or
setting the PRBS Enable bit [16-20.2] in the MDIO channel configuration registers. When the self-test function is
enabled, a PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data on the
transmit data bus is ignored during the PRBS test mode. The PRBS pattern is then fed through the transmit
circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester
(BERT), the receiver of another TLK3104SA channel, or looped back to the receive input of the same channel.
Since the PRBS is not really random but a predetermined sequence of ones and zeros, the data can be captured
and checked for errors by a BERT.
Result reporting of the PRBS test (PRBS_PASS) is available on each receive channel multifunction (MF[A-D])
pin. To enable the report of the PRBS tests, please refer to register 16.10:9. When PRBSEN = high and
SYNCEN = high, then PRBS_PASS goes low and stay low on the first occurrence of a bit error. Toggling
SYNCEN low then high resets the PRBS_PASS latch. If SYNCEN = low, then PRBS_PASS represents bit errors
in real time. Basically, whenever a bit error is detected, the PRBS_PASS goes low for one recovered clock, RCx,
half cycle.
MDIO management interface
The TLK3104SA supports the management data input/output (MDIO) Interface as defined in clause 22 of the
IEEE 802.3 ethernet specification. The MDIO allows register-based management and control of the serial links.
Normal operation of the TLK3104SA is possible without use of this interface since all of the essential signals
necessary for operations are accessible via the device pins. However, some additional features are accessible
only through the MDIO.
The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC).
The timing required to read from the internal registers is shown in Figure 15. The timing required to write to the
internal registers is shown in Figure 16.
MDC
MDIO
32 “1”s
Hi-Z
0
1
1
0
A4
A0
R4
R0
0
D15 D0
Preamble
SFD
PHY Address
Data
Idle
Register Address
Read Code
Turn Around
Figure 15. Management Interface Read Timing
18
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265