TLK3104SA_09 Datasheet, PDF (37/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
SSTL_2 CLASS 1/1.8V HSTL input timing requirements over recommended operating conditions
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
tsu
th
TDx[0:9] setup prior to TCx transition high or low
TDx[0:9] hold after TCx transition high or low
Timing relative to Vref, See Figure 22
MIN TYP MAX UNIT
480
ps
480
TCA, TCB,
TCC, TCD
tsu
th
Vref
th
tsu
TDx[0...9]
Figure 22. SSTL_2 CLASS1/1.8V HSTL Input Timing Requirements
MDIO timing requirements over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP† MAX UNIT
tp
MDC period
tsu MDIO setup to ↑ MDC
th
MDIO hold to ↑ MDC
† _{All typical values are at 25°C and with a nominal supply.}
See Figure 23
50 400 500 ns
10
ns
10
ns
MDC
MDIO
tp
tsu
th
Figure 23. MDIO Read/Write Timing
PACKAGE DISSIPATION RATING
AIR FLOW 0 m/s 1 m/s 2 m/s
θ_JA(C/W)
21
17.3 16.7
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