TLK3104SA_09 Datasheet, PDF (11/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
detailed description (continued)
data reception latency
For each channel, the serial-to-parallel data latency is the time from when the first bit arrives at the receiver input
until it is output in the aligned parallel word with RDx0 received as first bit, as shown in Figure 9. The minimum
latency t_{d(R_Latency)} is 46 bit times; the maximum is 166 bit times. There is approximately 20 bit times required
for the 8-B/10-B decoder.
RXxP
RXxN
RDx[0−7]
10 Bit Code Received
td(R_Latency)
Byte Received
RCx
Figure 9. Receiver Latency
auto detectable 1.8 V HSTL/SSTL_2 class 1 I/O
The transmit and receive data bus of the TLK3104SA are compatible with both high-speed transfer logic (HSTL)
scaled to 1.8 V supply and stub series terminated logic (SSTL) for 2.5 V class 1 buffer. The TLK3104 determines
which buffer technology to use by sensing the voltage level on the VDDQ supply pins at power up. If the voltage
on the VDDQ supply is between 2.3 and 2.7 V, the TLK3104 provides the necessary drive current to meet
SSTL_2 class 1 requirements. If the voltage on the VDDQ supply is between 1.6 and 2.0 V, the TLK3104
provides 1.8 V HSTL compatible signaling. During normal operation, the voltage level on the VDDQ pins must
not change.
All 1.8 V HSTL/SSTL_2 class 1 outputs are internally series terminated to provide direct connection to a 50-Ω
transmission line signaling environment (see Figure 26).
8-B/10-B encoder
All true serial interfaces require a method of encoding to insure sufficient transition density for the receiving PLL
to acquire and maintain lock. The encoding scheme also maintains the signal dc balance by keeping the number
of ones and zeros the same which allows for ac-coupled data transmission. The TLK3104SA uses the 8-B/10-B
encoding algorithm that is used by fibre channel and gigabit ethernet. This provides good transition density for
clock recovery and improves error checking. The 8-B/10-B encoder/decoder function is enabled for all 4
channels by the assertion of the CODE pin. When enabled, the TLK3104SA internally encodes and decodes
the data such that the user actually reads and writes 8-bit data on each channel.
When enabled, the 8-B/10-B encoder converts 8-bit wide data to a 10-bit wide encoded data character to
improve its transition density. This transmission code includes D-characters, used for transmitting data, and
K-characters, used for transmitting protocol information. Each K or D character code word can also have both
a positive and a negative disparity version. The disparity of a code word is selected by the encoder to balance
the running disparity of the serialized data stream.
The generation of K-characters to be transmitted on each channel is controlled by TDx8(KGEN). When KGEN
is asserted along with the 8 bits of data TDx[0..7], an 8-B/10-B K-character is transmitted. Similarly, reception
of K−characters is reported by RDx8(KFLAG). When KFLAG is asserted, the 8 bits of data on RDx[0..7] must
be interpreted as a K-character. The TLK3104SA transmits and receives all of the twelve valid K-characters
defined in Table 6. Table 4 provides additional transmit data control coding and descriptions that have been
proposed for 10 gigabits per second ethernet. Data patterns put on TDx[0:7] other than those defined in Table 6
when TDx8 is asserted results in an invalid K-character being transmitted which results in an code error at the
receiver.
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