TLK3104SA_09 Datasheet, PDF (14/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
receive synchronization and skew compensation
When the TLK3104SA is configured in channel sync mode, a FIFO is enabled in the parallel receive data path
on each channel to compensate for channel skew and clock phase tolerance differences between the recovered
clocks for each channel and the receive output clock, RCA, as is shown in Figure 10. This FIFO has a depth
of eleven bytes.
Protocol Device
TLK3104
Channel
Logic
Channel
Logic
Channel A
RCA
Channel B
RX
FIFO
Data A
RX
FIFO
RCLKA
Data B
RCLKB
Serdes
Core
Serdes
Core
Channel
Logic
Channel C
RX
FIFO
Data C
RCLKC
Serdes
Core
Channel
Logic
Channel D
RX
FIFO
Data D
RCLKD
Serdes
Core
Xtal OSC ^RFCP/RFCN
Figure 10. Receive and Reference Clock Relationship (Synchronized Channel Modes)
Channel synchronization is accomplished by alignment of the receive FIFOs on each channel to a K28.3
K-character sent during the interpacket gap (IPG) between data packets or during initial link synchronization.
The K28.3 code (referred to as the A or alignment code) is transmitted on the first column following the end of
the data packet as shown in Figure 11.
According to IEEE 802.3ae D2.0 clause 48, the channel alignment code is required to be retransmitted on the
same data column a minimum of every 16 or maximum of every 32 columns during the IPG or whenever there
is no data being transmitted to maintain channel synchronization. Because channel-to-channel skew is
predominantly static in nature, the TLK3104SA requires alignment only when system conditions change (such
as when line cards are hot plugged).
It is important to note that the protocol device must provide the appropriate data patterns (K28.3, K28.5, and
K28.0) on TDx(0:8) pins of the TLK3104SA for the proper generation of the K-characters necessary for lane
and channel synchronization.
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