TLK3104SA_09 Datasheet, PDF (30/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
TDB8
TDC8
TDD8
TDB9
TDC9
TDD9
H16, K16, R10
J13, J15, T10
1.8V HSTL/
SSTL_2 Input
1.8V HSTL/
SSTL_2 Input
Transmit data/KGEN, channels B−D, When PSYNC=low, data on this pin is clocked
on the rising and falling edge of the transmit channel clock (TCB, TCC, or TCD). When
PSYNC=high, data on this pin is clocked on the rising and falling edge of TCA.
When CODE = low, these pins are the 9th bit of a 8-B/10-B encoded byte to be
transmitted. When CODE = high, these pins act as the K-character generator
indicator. When driven high, these pins cause the data on TDx (0−7) to be encoded
into a K-character.
Transmit data pin, channels B−D, When PSYNC=low, data on this pin is clocked on
the rising and falling edge of the transmit channel clock (TCB, TCC, TCD). When
PSYNC=high, data on these pins are clocked on the rising and falling edge of TCA.
When CODE = low, these pins are the tenth bit of a 8-B/10-B encoded byte. When
CODE=high, these pins are ignored.
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