TLK3104SA_09 Datasheet, PDF (15/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
receive synchronization and skew compensation (continued)
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
Data Packet
Inter−Packet Gap (IPG)
Channel A ^{R K K R R K K R S d d d − − d d d d A K R K R K R R R K K R R K R R A}
Channel B ^{R K K R R K K R d d d d − − d d d T A K R K R K R R R K K R R K R R A}
Channel C ^{R K K R R K K R d d d d − − d d d K A K R K R K R R R K K R R K R R A}
Channel D ^{R K K R R K K R d d d d − − d d d K A K R K R K R R R K K R R K R R A}
S = Start of Packet
d = data
T = End of Packet
A = K28.3
K = K28.5
R = K28.0
Channel Alignment
Column
Figure 11. Channel Synchronization Using Alignment Code
According to IEEE 802.3ae D2.0 clause 46, a packet starts in channel A.
The repetition of the A pattern on each serial channel allows the FIFOs to remove or add the required phase
delay to align the data from all four channels for output on a single edge of the receive clock for channel A, RCA,
as shown in Figure 12.
RXAP/RXAN
Any Valid
Code
K28.3
K28.5
K28.0
R RX X X X X X X X X X AA AA A A A A A A KK K K K K K K K K R RR R RR RR R RK K K K
RXBP/RXBN
RR XX X XX X X X XX AA AA A AA A A A K K K K K KK KK KR RRR RR RR RRK KK K
RXCP/RXCN R R X X X X X X X X X X A A A A A A A A A A K K K K K K K K K K R R R R R R R R R R K K K K
RXDP/RXDN
RR XX X XX X X X X X AA AA A A A A A A K K K K K K K K KK R RR R RR RR RRK K KK
RCA
RDA[0−9]
Undefined
Undefined
A
K
R
RDB[0−9]
RDC[0−9]
Undefined
Undefined
A
Undefined
Undefined
A
K
R
K
R
RDD[0−9]
Undefined
Undefined
A
K
R
Figure 12. Channel Synchronization Using Alignment Code
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