TLK3104SA_09 Datasheet, PDF (27/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
Table 21. Channel Synchronization Status Register (Register 23)
BIT(s) NAME
23.15:5 Reserved
23.4 Channel sync flag
23.3 Channel D receive
FIFO collision error
23.2 Channel C receive
FIFO collision error
23.1 Channel B receive
FIFO collision error
23.0 Channel A receive
FIFO collision error
DESCRIPTION
Read returns 0.
1 = Channel synchronization circuit has detected a K28.3/A/code word on all channels.
0 = No /A/ has been detected.
After being read, this bit is reset to zero.
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error
After being read, this bit is reset to zero.
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error
After being read, this bit is reset to zero.
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error
After being read, this bit is reset to zero.
1 = Collision error is detected to cause the receive FIFO self reset.
0 = No error
After being read, this bit is reset to zero.
READ/WRITE
Read only
Read only
Read only
Read only
Read only
Read only
operating frequency range
The TLK3104SA is optimized for operation at a serial data rate of 3.125 Gbps. The TLK3104SA may operate
at a serial data rate between 2.5 Gbps and 3.125 Gbps. The external differential reference clock has an
operating frequency from 125 MHz to 156.25 MHz. The reference clock frequency must be within ±100 PPM
of the recovered clock and have less than 40 ps of jitter.
powerdown mode
When the ENABLE pin is held low the TLK3104SA goes into a low power quiescent state. In this state, all analog
and digital circuitry is disabled. In the power-down mode, the serial transmit and the receive data bus pins for
all channels are in a high impedance state.
loop-back testing
The TLK3104SA can provide a self-test function by enabling the internal loop-back path with the assertion of
LPENx for each channel or by setting the loopback bit [16-20:3] in the MDIO channel configuration registers.
Enabling this pin or bit causes serial transmitted data to be routed internally to the receiver for that channel (see
the block diagram of individual channel). The parallel data output can be compared to the parallel input data
for that channel to provide functional verification. The external differential output is held in a high-impedance
state during the loop-back testing.
power-on reset
Upon application of minimum valid power, the TLK3104SA generates an internal power-on reset. During the
power-on reset the receive data pins RDx[0..9] are held high (high-impedance) and the recovered receive clock
pins RC[A-D] are held low. The length of the power-on reset cycle is dependent upon the frequency of the
reference clock, RFCP/RFCN, but is less than 1 ms in duration.
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