TLK3104SA_09 Datasheet, PDF (28/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
Terminal Functions
TERMINAL
NAME
NO.
CLOCK PINS
RCA
A11
RCB, RCC, RCD
F17, M17,
U11
RFCP/RFCN
J3, J2
TCA
A10
F16, M16,
TCB, TCC, TCD _U10
SERIAL SIDE DATA PINS
RXAP/RXAN
RXBP/RXBN
RXCP/RXCN
RXDP/RXDN
B5, B6
F2, G2
M2, L2
T5, T6
TXAP/TXAN
TXBP/TXBN
TXCP/TXCN
TXDP/TXDN
D5, D6
F4, G4
M4, L4
P5, P6
PARALLEL SIDE DATA PINS
RDA(0−7)
C11, B11,
E12, D12,
C12, C13,
B13, A13
RDA8
B14
RDA9
A14
RDB(0−7)
C14, C15,
C16, C17,
D13, D15,
D16, E13
TYPE
1.8V
HSTL/SSTL_2
Output
1.8V
HSTL/SSTL_2
Output
PECL
compatible or
LVDS input
1.8V
HSTL/SSTL_2
input
1.8V
HSTL/SSTL_2
input
PECL
Compatible
Input
PECL
Compatible
Output
1.8V HSTL/
SSTL_2 Output
1.8V HSTL/
SSTL_2 Output
1.8V HSTL/
SSTL_2 Output
1.8V HSTL/
SSTL_2 Output
DESCRIPTION
Receive data clock, channel A—The data on RDA(0 - 9) is output off the rising and falling
edge of RCA. When PSYNC = high, RCA acts as the receive clock for all channels.
This pin has internal series termination to provide direct connection to a 50-Ω transmission
line.
Receive data clock, channels B−D—When PSYNC=low, the data on RDx(0−9) is output on
the rising and falling edges of the receive clocks. When PSYNC = high, these pins are held
low.
These pins have internal series termination to provide direct connection to a 50-Ω
transmission line.
Differential reference input clock—This differential pair accepts LVDS or PECL compatible
signals. When interfacing with 3.3-V PECL, ac-coupling is required. An on-chip 100-Ω
termination resistor is placed differentially between the pins. Internal biasing is provided.
Transmit data clock, channel A—The data on TDA(0−9) is latched on the rising and falling
edge of TCA. When PSYNC = high, TCA acts as the transmit clock for all channels.
Transmit data clock, channels B−D—When PSYNC=low, the data on TDx(0−9) is latched
on the rising and falling edges of the transmit clocks. When PSYNC = high, these pins are
undefined.
Receive differential pairs, channel A−D, High speed serial inputs with on-chip 100-Ω
differential termination. Each input pair is terminated differentially across an on-chip 100-Ω
resistor (see Figures 23 and 24).
Transmit differential pairs, channel A−D, High speed serial outputs.
Receive data pins, channel A, Parallel data on this bus is valid on the rising and falling edge
of RCA.
These pins have internal series termination to provide direct connection to a 50-Ω
transmission line.
Receive data/K-flag, channel A When CODE = low, this pin is the 9th bit of a received
8-B/10-B encoded byte. When CODE = high, this pin acts as the K- character flag. When
high, this indicates the data on RDA(0−7) is a valid K–character. Data on this pin is valid on
the rising and falling edge of RCA.
These pins have internal series termination to provide direct connection to a 50-Ω
transmission line.
Receive data pin/error detect, channel A, When CODE = low, this pin is the 10th bit of a
8-B/10-B encoded byte. When CODE = high, this pin goes high to signify the occurrence of
either a disparity error or an invalid code word during the decoding of the received data.
Data on this pin is valid on the rising and falling edge of RCA.
These pins have internal series termination to provide direct connection to a 50-Ω
transmission line.
Receive data pins, channels B−D, When PSYNC=low, parallel data on these buses is valid
on the rising and falling edge of the recovered data clock (RCB, RCC, or RCD). When
PSYNC=high, data on each bus is valid on the rising and falling edge of RCA. These pins
are series terminated to provide direct connection to a 50-Ω transmission line.
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