TLK3104SA_09 Datasheet, PDF (36/43 Pages) Texas Instruments – QUAD 3.125 Dbps SERIAL TRANSCEIVER

TLK3104SA
QUAD 3.125 Gbps SERIAL TRANSCEIVER
SCAS651B-− AUGUST 2000 − REVISED SEPTEMBER 2001
600
0
−600
0.175
0.825 1
Unit Interval
Figure 18. Transmit Template
t(J_IDR)
100
0
−100
0.275
0.725
1
Unit Interval
Figure 19. Receive Template
t(J_R)
t(J_R)
t(J_TOL)
NOTE: t(J_TOL)= t(J_R) + t(J_IDR), where t(J_TOL) is the receive jitter tolerance,
t(J_IDR) is the received deterministic jitter, and t(J_R) is the Gaussian
random edge jitter distribution at a maximum BER = 10-12.
Figure 20. Input Jitter
SSTL_2 CLASS 1/1.8V HSTL output switching characteristics
PARAMETER
TEST CONDITIONS
tsu
RDx[0:9] setup prior to RCx transition high or low
Timing relative to 0.5 × V(DDQ),
th
RDx[0:9] hold after RCx transition high or low
See Figure 21
MIN TYP MAX UNIT
960
ps
960
RCA, RCB,
RCC, RCD
tsu
th
th
tsu
RDx[0...9]
Figure 21. SSTL_2 CLASS1/1.8V HSTL Output Timing Requirements
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