MSP430FR2033 Datasheet, PDF (8/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Figure 4-3 shows the 48-pin G48 package.
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P3.1
1
P3.0
2
P7.3
3
P7.2
4
P7.1
5
P7.0
6
P4.7
7
P4.6
8
P4.5
9
P4.4
10
P4.3
11
P4.2/XOUT
12
P4.1/XIN
13
DVSS
14
DVCC
15
RST/NMI/SBWTDIO
16
TEST/SBWTCK
17
P4.0/TA1.1
18
P1.7/TA0.1/TDO/A7
19
P1.6/TA0.2/TDI/TCLK/A6
20
P1.5/TA0CLK/TMS/A5
21
P1.4/MCLK/TCK/A4/VREF+
22
P1.3/UCA0STE/A3
23
P1.2/UCA0CLK/A2
24
48
P3.2
47
P3.3
46
P3.4
45
P3.5
44
P3.6
43
P3.7
42
P6.0
41
P6.1
40
P6.2
39
P6.3
38
P2.0
37
P2.1
36
P2.2
35
P2.3
34
P2.4
33
P2.5
32
P2.6
31
P2.7
30
P5.0/UCB0STE
29
P5.1/UCB0CLK
28
P5.2/UCB0SIMO/UCB0SDA
27
P5.3/UCB0SOMI/UCB0SCL
26
P1.0/UCA0TXD/UCA0SIMO/A0/Veref–
25
P1.1/UCA0RXD/UCA0SOMI/A1/Veref+
Figure 4-3. 48-Pin DGG (TSSOP) Designation (Top View)
8
Terminal Configuration and Functions
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