MSP430FR2033 Datasheet, PDF (24/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
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5.12.6 eUSCI
Table 5-11. eUSCI (UART Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_eUSCI
PARAMETER
eUSCI input clock frequency
TEST CONDITIONS
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
V_CC
MIN
2 V, 3 V
f_BITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
2 V, 3 V
MAX UNIT
16 MHz
5 MHz
Table 5-12. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
V_CC
TYP UNIT
12
t_t
UART receive deglitch time ⁽¹⁾
UCGLITx = 1
UCGLITx = 2
2 V, 3 V
40
ns
68
UCGLITx = 3
110
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized, their duration should exceed the maximum specification of the deglitch time.
Table 5-13. eUSCI (SPI Master Mode) Recommended Operating Conditions
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
f_eUSCI
eUSCI input clock frequency
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
MAX UNIT
8 MHz
Table 5-14. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
t_STE,LEAD
PARAMETER
STE lead time, STE active to clock
TEST CONDITIONS
V_CC
UCSTEM = 1, UCMODEx = 01 or 10
MIN MAX UNIT
1
UCxCLK
cycles
t_STE,LAG
STE lag time, Last clock to STE inactive UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
t_SU,MI
SOMI input data setup time
2V
45
ns
3V
35
t_HD,MI
SOMI input data hold time
2V
0
ns
3V
0
t_VALID,MO
SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2V
3V
20
ns
20
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF
2V
0
ns
3V
0
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-9 and Figure 5-10.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-9 and Figure 5-10.
24
Specifications
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