MSP430FR2033 Datasheet, PDF (18/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5.12 Timing and Switching Characteristics
5.12.1 Power Supply Sequencing
V
Power Cycle Reset
VSVS+
VSVS–
SVS Reset
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BOR Reset
VBOR
tBOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V_{BOR, safe}
t_{BOR, safe}
I_SVSH,AM
I_SVSH,LPM
V_SVSH-
V_SVSH+
V_{SVSH_hys}
t_{PD,SVSH, AM}
t_{PD,SVSH, LPM}
V_{REF, 1.2V}
PARAMETER
Safe BOR power-down level⁽¹⁾
Safe BOR reset delay⁽²⁾
SVS_H current consumption, active mode
SVS_H current consumption, low-power modes
SVS_H power-down level
SVS_H power-up level
SVS_H hysteresis
SVS_H propagation delay, active mode
SVS_H propagation delay, low-power modes
1.2-V REF voltage⁽³⁾
TEST CONDITIONS
V_CC = 3.6 V
V_CC = 3.6 V
MIN
0.1
10
1.71
1.76
1.158
TYP
240
1.81
1.88
70
1.200
MAX UNIT
V
ms
1.5 µA
nA
1.87 V
1.99 V
mV
10 µs
100 µs
1.242 V
(1) A safe BOR can be correctly generated only if DVCC drops below this voltage before it rises.
(2) When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches V_SVSH+.
(3) This is a characterized result with external 1-mA load to ground from –40°C to +85°C.
18
Specifications
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