MSP430FR2033 Datasheet, PDF (39/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-8. System Module Interrupt Vector Registers (continued)
INTERRUPT VECTOR
REGISTER
ADDRESS
SYSSNIV, System NMI
015Ch
SYSUNIV, User NMI
015Ah
INTERRUPT EVENT
No interrupt pending
SVS low-power reset entry
Uncorrectable FRAM bit error detection
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VMAIFG Vacant memory access
JMBINIFG JTAG mailbox input
JMBOUTIFG JTAG mailbox output
Correctable FRAM bit error detection
Reserved
No interrupt pending
NMIFG NMI pin or SVS_H event
OFIFG oscillator fault
Reserved
VALUE
00h
02h
04h
06h
08h
0Ah
0Ch
0Eh
10h
12h
14h
16h
18h
1Ah to 1Eh
00h
02h
04h
06h to 1Eh
PRIORITY
Highest
Lowest
Highest
Lowest
6.9.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x¹⁶ + x¹² + x⁵ + 1.
6.9.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I²C communications.
Additionally, eUSCI_A supports automatic baud-rate detection and IrDA.
Table 6-9. eUSCI Pin Configurations
eUSCI_A0
eUSCI_B0
PIN
P1.0
P1.1
P1.2
P1.3
PIN
P5.0
P5.1
P5.2
P5.3
UART
TXD
RXD
I²C
SDA
SCL
SPI
SIMO
SOMI
SCLK
STE
SPI
STE
SCLK
SIMO
SOMI
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