MSP430FR2033 Datasheet, PDF (65/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-41. Port P5, P6 Registers (Base Address: 0240h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P5 input
P5IN
00h
Port P5 output
P5OUT
02h
Port P5 direction
P5DIR
04h
Port P5 pulling register enable
P5REN
06h
Port P5 selection 0
P5SEL0
0Ah
Port P6 input
P6IN
01h
Port P6 output
P6OUT
03h
Port P6 direction
P6DIR
05h
Port P6 pulling register enable
Port P6 selection 0⁽¹⁾
P6REN
07h
P6SEL0
0Bh
(1) Port P6 selection register does not feature any valid bits. P6SEL0 presents for 16-bit Port C operation with P5SEL0.
Table 6-42. Port P7, P8 Registers (Base Address: 0260h)
REGISTER DESCRIPTION
REGISTER
OFFSET
Port P7 input
P7IN
00h
Port P7 output
P7OUT
02h
Port P7 direction
P7DIR
04h
Port P7 pulling register enable
Port P7 selection 0⁽¹⁾
P7REN
06h
P7SEL0
0Ah
Port P8 input
P8IN
01h
Port P8 output
P8OUT
03h
Port P8 direction
P8DIR
05h
Port P8 pulling register enable
P8REN
07h
Port P8 selection 0
P8SEL0
0Bh
(1) Port P7 selection register does not feature any valid bits. P7SEL0 presents for 16-bit Port D operation with P8SEL0.
Table 6-43. Capacitive Touch I/O Registers (Base Address: 02E0h)
REGISTER DESCRIPTION
Capacitive Touch I/O 0 control
REGISTER
CAPTIO0CTL
OFFSET
0Eh
Table 6-44. Timer0_A3 Registers (Base Address: 0300h)
REGISTER DESCRIPTION
TA0 control
Capture/compare control 0
Capture/compare control 1
Capture/compare control 2
TA0 counter register
Capture/compare register 0
Capture/compare register 1
Capture/compare register 2
TA0 expansion register 0
TA0 interrupt vector
REGISTER
TA0CTL
TA0CCTL0
TA0CCTL1
TA0CCTL2
TA0R
TA0CCR0
TA0CCR1
TA0CCR2
TA0EX0
TA0IV
OFFSET
00h
02h
04h
06h
10h
12h
14h
16h
20h
2Eh
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