MSP430FR2033 Datasheet, PDF (45/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-14. Port P1 Pin Functions
PIN NAME (P1.x)
x
FUNCTION
CONTROL BITS AND SIGNALS⁽¹⁾
P1DIR.x
P1SEL0.x
ADCPCTLx ⁽²⁾
JTAG
P1.0 (I/O)
I: 0; O: 1
0
0
N/A
P1.0/UCA0TXD/UCA0SIMO/A0
0 UCA0TXD/UCA0SIMO
X
1
0
N/A
A0
X
X
1 (x = 0)
N/A
P1.1 (I/O)
I: 0; O: 1
0
0
N/A
P1.1/UCA0RXD/UCA0SOMI/A1
1 UCA0RXD/UCA0SOMI
X
1
0
N/A
A1
X
X
1 (x = 1)
N/A
P1.2 (I/O)
I: 0; O: 1
0
0
N/A
P1.2/UCA0CLK/A2
2 UCA0CLK
X
1
0
N/A
A2
X
X
1 (x = 2)
N/A
P1.3 (I/O)
I: 0; O: 1
0
0
N/A
P1.3/UCA0STE/A3
3 UCA0STE
X
1
0
N/A
A3
X
X
1 (x = 3)
N/A
P1.4 (I/O)
I: 0; O: 1
0
0
Disabled
P1.4/MCLK/TCK/A4/VREF+
VSS
4 MCLK
0
1
1
0
Disabled
A4, VREF+
X
X
1 (x = 4)
Disabled
JTAG TCK
X
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
0
0
Disabled
P1.5/TA0CLK/TMS/A5
TA0CLK
5 VSS
0
1
1
0
Disabled
A5
X
X
1 (x = 5)
Disabled
JTAG TMS
X
X
X
TMS
P1.6 (I/O)
I: 0; O: 1
0
0
Disabled
P1.6/TA0.2/TDI/TCLK/A6
TA0.CCI2A
6 TA0.2
0
1
1
0
Disabled
A6
X
X
1 (x = 6)
Disabled
JTAG TDI/TCLK
X
X
X
TDI/TCLK
P1.7 (I/O)
I: 0; O: 1
0
0
Disabled
P1.7/TA0.1/TDO/A7
TA0.CCI1A
7 TA0.1
0
1
1
0
Disabled
A7
X
X
1 (x = 7)
Disabled
JTAG TDO
X
X
X
TDO
(1) X = don't care
(2) Setting the ADCPCTLx bit in SYSCFG2 register disables both the output driver and the input Schmitt trigger to prevent leakage when
analog signals are applied.
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Detailed Description
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