MSP430FR2033 Datasheet, PDF (13/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
5 Specifications
5.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Voltage applied at DVCC pin to V_SS
Voltage applied to any pin⁽²⁾
–0.3
4.1
V
–0.3
V_CC + 0.3
(4.1 Maximum)
V
Diode current at any device pin
±2
mA
Maximum junction temperature, T_J
Storage temperature, T_stg(3)
85
°C
–40
125
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V_SS.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
V_(ESD) Electrostatic discharge _{Charged-device model (CDM), per JEDEC specification JESD22-C101(2)}
VALUE
±1000
±250
UNIT
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V
may actually have higher performance.
5.3 Recommended Operating Conditions
Typical values are specified at V_CC = 3.3 V and T_A = 25°C (unless otherwise noted)
V_CC
V_SS
T_A
T_J
C_DVCC
f_SYSTEM
Supply voltage applied at DVCC pin^(1)(2)(3)
Supply voltage applied at DVSS pin
Operating free-air temperature
Operating junction temperature
Recommended capacitor at DVCC⁽⁴⁾
Processor frequency (maximum MCLK frequency)⁽³⁾⁽⁵⁾
No FRAM wait states
(NWAITSx = 0)
With FRAM wait states
(NWAITSx = 1)⁽⁶⁾
MIN NOM MAX UNIT
1.8
3.6 V
0
V
–40
85 °C
–40
85 °C
4.7
10
µF
0
8
MHz
0
16 ⁽⁷⁾
f_ACLK
f_SMCLK
Maximum ACLK frequency
Maximum SMCLK frequency
40 kHz
16⁽⁷⁾ MHz
(1) Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
(2) Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
(3) The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in Table 5-1.
(4) A capacitor tolerance of ±20% or better is required.
(5) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(6) Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
(7) If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
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Specifications
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