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MSP430FR2033 Datasheet, PDF (32/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers
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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6 Detailed Description
6.1 CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.2 Operating Modes
The MSP430 has one active mode and several software selectable low-power modes of operation. An
interrupt event can wake up the device from low-power mode LPM0 or LPM3, service the request, and
restore back to the low-power mode on return from the interrupt program. Low-power modes LPM3.5 and
LPM4.5 disable the core supply to minimize power consumption.
MODE
Maximum System Clock
Power Consumption at 25°C, 3 V
Wake-up time
Wake-up events
Power
Clock
Core
Regulator
SVS
Brown Out
MCLK
SMCLK
FLL
DCO
MODCLK
REFO
ACLK
XT1CLK
VLOCLK
CPU
FRAM
RAM
Backup Memory(1)
Table 6-1. Operating Modes
AM
ACTIVE
MODE
16 MHz
126 µA/MHz
N/A
N/A
Full
Regulation
On
On
Active
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
On
On
On
On
LPM0
CPU OFF
16 MHz
20 µA/MHz
instant
All
Full
Regulation
On
On
Off
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Off
On
On
On
LPM3
STANDBY
40 kHz
1.2 µA
10 µs
All
Partial Power
Down
Optional
On
Off
Off
Off
Off
Off
Optional
Optional
Optional
Optional
Off
Off
On
On
LPM4
OFF
0
0.6 µA
without SVS
10 µs
I/O
Partial Power
Down
Optional
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
LPM3.5
ONLY RTC
COUNTER
40 kHz
0.77 µA with
RTC only
150 µs
RTC Counter,
I/O
Partial Power
Down
Optional
On
Off
Off
Off
Off
Off
Off
Off
Optional
Optional
Off
Off
Off
On
LPM4.5
SHUTDOWN
0
13 nA
without SVS
150 µs
I/O
Power Down
Optional
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
(1) Backup memory contains one 32-byte register in the peripheral memory space. Refer to Table 6-31 and Table 6-49 for its memory
allocation.
32
Detailed Description
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