MSP430FR2033 Datasheet, PDF (26/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
Table 5-15. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
t_STE,LEAD
PARAMETER
STE lead time, STE active to clock
TEST CONDITIONS
V_CC
MIN MAX UNIT
2V
55
ns
3V
45
t_STE,LAG
STE lag time, Last clock to STE inactive
2V
20
ns
3V
20
t_STE,ACC
STE access time, STE active to SOMI data out
2V
65
ns
3V
40
t_STE,DIS
STE disable time, STE inactive to SOMI high
impedance
2V
40
ns
3V
35
t_SU,SI
SIMO input data setup time
2V
4
ns
3V
4
t_HD,SI
SIMO input data hold time
2V
12
ns
3V
12
t_VALID,SO
SOMI output data valid time⁽²⁾
UCLK edge to SOMI valid,
2V
C_L = 20 pF
3V
65
ns
40
t_HD,SO
SOMI output data hold time ⁽³⁾
C_L = 20 pF
2V
5
ns
3V
5
(1) f_UCxCLK = 1/2t_LO/HI with t_LO/HI ≥ max(t_{VALID,MO(Master)} + t_SU,SI(eUSCI), t_{SU,MI(Master)} + t_{VALID,SO(eUSCI)}).
For the master parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-11 and Figure 5-12.
26
Specifications
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