MSP430FR2033 Datasheet, PDF (62/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
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6.11.1 Peripheral File Map
Table 6-31 shows the base address and the memory size of the register region for each peripheral, and
Table 6-32 through Table 6-50 show all of the available registers for each peripheral and their address
offsets.
MODULE NAME
Special Functions (See Table 6-32)
PMM (See Table 6-33)
SYS (See Table 6-34)
CS (See Table 6-35)
FRAM (See Table 6-36)
CRC (See Table 6-37)
WDT (See Table 6-38)
Port P1, P2 (See Table 6-39)
Port P3, P4 (See Table 6-40)
Port P5, P6 (See Table 6-41)
Port P7, P8 (See Table 6-42)
Capacitive Touch I/O (See Table 6-43)
Timer0_A3 (See Table 6-44)
Timer1_A3 (See Table 6-45)
RTC (See Table 6-46)
eUSCI_A0 (See Table 6-47)
eUSCI_B0 (See Table 6-48)
Backup Memory (See Table 6-49)
ADC (See Table 6-50)
Table 6-31. Peripherals Summary
BASE ADDRESS
0100h
0120h
0140h
0180h
01A0h
01C0h
01CCh
0200h
0220h
0240h
0260h
02E0h
0300h
0340h
03C0h
0500h
0540h
0660h
0700h
SIZE
0010h
0020h
0030h
0020h
0010h
0008h
0002h
0020h
0020h
0020h
0020h
0010h
0030h
0030h
0010h
0020h
0030h
0020h
0040h
62
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