MSP430FR2033 Datasheet, PDF (37/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
Table 6-6. Clock Distribution
CLOCK
SOURCE
SELECT
BITS
MCLK
SMCLK
ACLK
MODCLK XT1CLK⁽¹⁾ VLOCLK
EXTERNAL PIN
Frequency
Range
DC to
16 MHz
DC to
16 MHz
DC to
40 kHz
5 MHz ±10%
DC to
40 kHz
10 kHz
±50%
CPU
N/A
Default
FRAM
N/A
Default
RAM
N/A
Default
CRC
N/A
Default
I/O
N/A
Default
TA0
TASSEL
10b
01b
00b (TA0CLK pin)
TA1
TASSEL
10b
01b
00b (TA1CLK pin)
eUSCI_A0
UCSSEL
10b or 11b
01b
00b (UCA0CLK pin)
eUSCI_B0
UCSSEL
10b or 11b
01b
00b (UCB0CLK pin)
WDT
WDTSSEL
00b
01b
10b
ADC
ADCSSEL
11b
01b
00b
RTC
RTCSS
01b
10b
11b
(1) To enable XT1 functionality, configure P4SEL0.1 (XIN) and P4SEL0.2 (XOUT) before configuring the Clock System registers.
6.9.3 General-Purpose Input/Output Port (I/O)
There are up to 60 I/O ports implemented, depending on the package.
• P1, P2, P3, P4, P5, P6, and P7 are full 8-bit ports; P8 has 4 bits implemented.
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wake-up input capability is available for P1 and P2.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch I/O functionality is supported on all pins.
NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, refer to the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445)
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Detailed Description
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