MSP430FR2033 Datasheet, PDF (40/89 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR2033, MSP430FR2032
SLASE45B – OCTOBER 2014 – REVISED AUGUST 2015
www.ti.com
6.9.8 Timers (Timer0_A3, Timer1_A3)
The Timer0_A3 and Timer1_A3 modules are 16-bit timers and counters with three capture/compare
registers each. Each timer can support multiple captures or compares, PWM outputs, and interval timing.
Each timer has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow
conditions and from each of the capture/compare registers. The CCR0 registers on both TA0 and TA1 are
not externally connected and can only be used for hardware period timing and interrupt generation. In Up
mode, they can be used to set the overflow value of the counter.
PORT PIN
P1.5
P1.7
P1.6
Table 6-10. Timer0_A3 Signal Connections
DEVICE INPUT
SIGNAL
TA0CLK
ACLK (internal)
SMCLK (internal)
From Capacitive
Touch I/O (internal)
MODULE INPUT
NAME
TACLK
ACLK
SMCLK
INCLK
CCI0A
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCI0B
CCR0
TA0
DVSS
GND
DVCC
VCC
TA0.1
CCI1A
From RTC (internal)
CCI1B
CCR1
TA1
DVSS
GND
DVCC
VCC
TA0.2
CCI2A
From Capacitive
Touch I/O (internal)
CCI2B
CCR2
TA2
DVSS
DVCC
GND
VCC
DEVICE OUTPUT
SIGNAL
Timer1_A3 CCI0B
input
TA0.1
Timer1_A3 CCI1B
input
TA0.2
Timer1_A3 INCLK
Timer1_A3 CCI2B
input,
IR Input
40
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