LM3S6C11 Datasheet, PDF (588/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Synchronous Serial Interface (SSI)
SSIClk period, meaning that data is captured on the falling edges and propagated on the rising
edges of the SSIClk signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSIFss
line is returned to its idle High state one SSIClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSIFss signal must be pulsed
High between each data word transfer because the slave select pin freezes the data in its serial
peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master
device must raise the SSIFss pin of the slave device between each data transfer to enable the
serial peripheral data write. On completion of the continuous transfer, the SSIFss pin is returned
to its idle state one SSIClk period after the last bit has been captured.
13.3.4.6
Freescale SPI Frame Format with SPO=1 and SPH=1
The transfer signal sequence for Freescale SPI format with SPO=1 and SPH=1 is shown in Figure
13-9 on page 588, which covers both single and continuous transfers.
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1
SSIClk
SSIFss
SSIRx
SSITx
Q MSB
MSB
4 to 16 bits
LSB Q
LSB
Note: Q is undefined.
In this configuration, during idle periods:
■ SSIClk is forced High
■ SSIFss is forced High
■ The transmit data line SSITx is arbitrarily forced Low
■ When the SSI is configured as a master, it enables the SSIClk pad
■ When the SSI is configured as a slave, it disables the SSIClk pad
If the SSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by
the SSIFss master signal being driven Low. The master SSITx output pad is enabled. After an
additional one-half SSIClk period, both master and slave data are enabled onto their respective
transmission lines. At the same time, SSIClk is enabled with a falling edge transition. Data is then
captured on the rising edges and propagated on the falling edges of the SSIClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSIFss line is
returned to its idle high state one SSIClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSIFss pin remains in its active Low state until the
final bit of the last word has been captured and then returns to its idle state as described above.
588
July 24, 2012
Texas Instruments-Production Data