LM3S6C11 Datasheet, PDF (24/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

Table of Contents
OBSOLETE: TI has discontinued production of this device.
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 651
I²C Slave Control/Status (I2CSCSR), offset 0x804 ........................................................... 652
I²C Slave Data (I2CSDR), offset 0x808 ........................................................................... 654
I²C Slave Interrupt Mask (I2CSIMR), offset 0x80C ........................................................... 655
I²C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 ................................................... 656
I²C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 .............................................. 657
I²C Slave Interrupt Clear (I2CSICR), offset 0x818 ............................................................ 658
Ethernet Controller ...................................................................................................................... 659
Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 ....... 673
Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 676
Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 678
Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 680
Register 5: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 682
Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 684
Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 685
Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 686
Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 688
Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 690
Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 691
Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 692
Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 693
Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 694
Register 15: Ethernet MAC LED Encoding (MACLED), offset 0x040 .................................................... 695
Register 16: Ethernet PHY MDIX (MDIX), offset 0x044 ....................................................................... 697
Register 17: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 698
Register 18: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 700
Register 19: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 702
Register 20: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 703
Register 21: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address
0x04 ............................................................................................................................. 704
Register 22: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability
(MR5), address 0x05 ..................................................................................................... 706
Register 23: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address
0x06 ............................................................................................................................. 708
Register 24: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 709
Register 25: Ethernet PHY Management Register 17 – Mode Control/Status (MR17), address 0x11 ...... 710
Register 26: Ethernet PHY Management Register 27 – Special Control/Status (MR27), address
0x1B ............................................................................................................................. 712
Register 27: Ethernet PHY Management Register 29 – Interrupt Status (MR29), address 0x1D ............. 713
Register 28: Ethernet PHY Management Register 30 – Interrupt Mask (MR30), address 0x1E ............... 715
Register 29: Ethernet PHY Management Register 31 – PHY Special Control/Status (MR31), address
0x1F ............................................................................................................................. 717
Analog Comparators ................................................................................................................... 718
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 .................................. 723
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ....................................... 724
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ......................................... 725
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 ....................... 726
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 ..................................................... 727
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July 24, 2012
Texas Instruments-Production Data