LM3S6C11 Datasheet, PDF (157/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6C11 Microcontroller
4.1 Block Diagram
Figure 4-1. JTAG Module Block Diagram
TCK
TMS
TAP Controller
TDI
Instruction Register (IR)
BYPASS Data Register
Boundary Scan Data Register
IDCODE Data Register
ABORT Data Register
DPACC Data Register
APACC Data Register
TDO
Cortex-M3
Debug
Port
4.2 Signal Description
The following table lists the external signals of the JTAG/SWD controller and describes the function
of each. The JTAG/SWD controller signals are alternate functions for some GPIO signals, however
note that the reset state of the pins is for the JTAG/SWD function. The JTAG/SWD controller signals
are under commit protection and require a special process to be configured as GPIOs, see “Commit
Control” on page 399. The column in the table below titled "Pin Mux/Pin Assignment" lists the GPIO
pin placement for the JTAG/SWD controller signals. The AFSEL bit in the GPIO Alternate Function
Select (GPIOAFSEL) register (page 413) is set to choose the JTAG/SWD function. The number in
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 430) to assign the JTAG/SWD controller signals to the specified GPIO
port pin. For more information on configuring GPIOs, see “General-Purpose Input/Outputs
(GPIOs)” on page 392.
Table 4-1. JTAG_SWD_SWO Signals (100LQFP)
Pin Name
SWCLK
SWDIO
SWO
TCK
TDI
TDO
Pin Number Pin Mux / Pin
Assignment
80
PC0 (3)
79
PC1 (3)
77
PC3 (3)
80
PC0 (3)
78
PC2 (3)
77
PC3 (3)
Pin Type
I
I/O
O
I
I
O
Buffer Type^a Description
TTL
JTAG/SWD CLK.
TTL
JTAG TMS and SWDIO.
TTL
JTAG TDO and SWO.
TTL
JTAG/SWD CLK.
TTL
JTAG TDI.
TTL
JTAG TDO and SWO.
July 24, 2012
157
Texas Instruments-Production Data