LM3S6C11 Datasheet, PDF (581/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6C11 Microcontroller
parentheses is the encoding that must be programmed into the PMCn field in the GPIO Port Control
(GPIOPCTL) register (page 430) to assign the SSI signal to the specified GPIO port pin. For more
information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 392.
Table 13-1. SSI Signals (100LQFP)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
SSI0Clk
28
PA2 (1)
I/O
TTL
SSI module 0 clock
SSI0Fss
29
PA3 (1)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
30
PA4 (1)
I
TTL
SSI module 0 receive
SSI0Tx
31
PA5 (1)
O
TTL
SSI module 0 transmit
SSI1Clk
60
PF2 (9)
I/O
72
PE0 (2)
TTL
SSI module 1 clock
SSI1Fss
59
PF3 (9)
I/O
73
PE1 (2)
TTL
SSI module 1 frame signal
SSI1Rx
74
PE2 (2)
I
TTL
SSI module 1 receive
SSI1Tx
75
PE3 (2)
O
TTL
SSI module 1 transmit
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 13-2. SSI Signals (108BGA)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
SSI0Clk
M4
PA2 (1)
I/O
TTL
SSI module 0 clock
SSI0Fss
L4
PA3 (1)
I/O
TTL
SSI module 0 frame signal
SSI0Rx
L5
PA4 (1)
I
TTL
SSI module 0 receive
SSI0Tx
M5
PA5 (1)
O
TTL
SSI module 0 transmit
SSI1Clk
J11
PF2 (9)
I/O
A11
PE0 (2)
TTL
SSI module 1 clock
SSI1Fss
J12
PF3 (9)
I/O
B12
PE1 (2)
TTL
SSI module 1 frame signal
SSI1Rx
B11
PE2 (2)
I
TTL
SSI module 1 receive
SSI1Tx
A12
PE3 (2)
O
TTL
SSI module 1 transmit
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes. The SSI also supports the µDMA interface. The transmit and receive FIFOs
can be programmed as destination/source addresses in the µDMA module. µDMA operation is
enabled by setting the appropriate bit(s) in the SSIDMACTL register (see page 608).
13.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
July 24, 2012
581
Texas Instruments-Production Data