LM3S6C11 Datasheet, PDF (5/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6C11 Microcontroller
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Hibernation Module .............................................................................................. 259
6.1 Block Diagram ............................................................................................................ 260
6.2 Signal Description ....................................................................................................... 260
6.3 Functional Description ................................................................................................. 261
6.3.1 Register Access Timing ............................................................................................... 261
6.3.2 Hibernation Clock Source ............................................................................................ 262
6.3.3 System Implementation ............................................................................................... 263
6.3.4 Battery Management ................................................................................................... 264
6.3.5 Real-Time Clock .......................................................................................................... 264
6.3.6 Battery-Backed Memory .............................................................................................. 265
6.3.7 Power Control Using HIB ............................................................................................. 265
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 265
6.3.9 Initiating Hibernate ...................................................................................................... 265
6.3.10 Waking from Hibernate ................................................................................................ 265
6.3.11 Interrupts and Status ................................................................................................... 266
6.4 Initialization and Configuration ..................................................................................... 266
6.4.1 Initialization ................................................................................................................. 266
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 267
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 267
6.4.4 External Wake-Up from Hibernation .............................................................................. 268
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 268
6.5 Register Map .............................................................................................................. 268
6.6 Register Descriptions .................................................................................................. 269
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 286
Block Diagram ............................................................................................................ 286
Functional Description ................................................................................................. 286
SRAM ........................................................................................................................ 287
ROM .......................................................................................................................... 287
Flash Memory ............................................................................................................. 289
Register Map .............................................................................................................. 294
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 296
Memory Register Descriptions (System Control Offset) .................................................. 308
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Micro Direct Memory Access (μDMA) ................................................................ 332
8.1 Block Diagram ............................................................................................................ 333
8.2 Functional Description ................................................................................................. 333
8.2.1 Channel Assignments .................................................................................................. 334
8.2.2 Priority ........................................................................................................................ 335
8.2.3 Arbitration Size ............................................................................................................ 335
8.2.4 Request Types ............................................................................................................ 335
8.2.5 Channel Configuration ................................................................................................. 336
8.2.6 Transfer Modes ........................................................................................................... 338
8.2.7 Transfer Size and Increment ........................................................................................ 346
8.2.8 Peripheral Interface ..................................................................................................... 346
8.2.9 Software Request ........................................................................................................ 346
8.2.10 Interrupts and Errors .................................................................................................... 347
8.3 Initialization and Configuration ..................................................................................... 347
8.3.1 Module Initialization ..................................................................................................... 347
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 348
July 24, 2012
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Texas Instruments-Production Data