LM3S6C11 Datasheet, PDF (22/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

Table of Contents
OBSOLETE: TI has discontinued production of this device.
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 480
GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 481
GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 482
GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 483
GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 484
GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 485
GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 486
GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 487
GPTM Timer B (GPTMTBR), offset 0x04C ....................................................................... 488
GPTM Timer A Value (GPTMTAV), offset 0x050 ............................................................... 489
GPTM Timer B Value (GPTMTBV), offset 0x054 .............................................................. 490
Watchdog Timers ......................................................................................................................... 491
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 495
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 496
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 497
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 499
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 500
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 501
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 502
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 503
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 504
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 505
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 506
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 507
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 508
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 509
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 510
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 511
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 512
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 513
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 514
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 515
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 516
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 530
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 532
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 535
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 538
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 539
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 540
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 541
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 543
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 547
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 549
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 553
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 557
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 561
Register 14: UART DMA Control (UARTDMACTL), offset 0x048 .......................................................... 563
Register 15: UART LIN Control (UARTLCTL), offset 0x090 ................................................................. 564
22
July 24, 2012
Texas Instruments-Production Data