LM3S6C11 Datasheet, PDF (251/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6C11 Microcontroller
Bit/Field
13
12:7
6
5
4
3
2
1
0
Name
UDMA
reserved
GPIOG
GPIOF
GPIOE
GPIOD
GPIOC
GPIOB
GPIOA
Type
R/W
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
Description
Micro-DMA Clock Gating Control
This bit controls the clock gating for micro-DMA. If set, the module
receives a clock and functions. Otherwise, the module is unclocked and
disabled. If the module is unclocked, a read or write to the module
generates a bus fault.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Port G Clock Gating Control
This bit controls the clock gating for Port G. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port F Clock Gating Control
This bit controls the clock gating for Port F. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port E Clock Gating Control
Port E Clock Gating Control. This bit controls the clock gating for Port
E. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
Port D Clock Gating Control
Port D Clock Gating Control. This bit controls the clock gating for Port
D. If set, the module receives a clock and functions. Otherwise, the
module is unclocked and disabled. If the module is unclocked, a read
or write to the module generates a bus fault.
Port C Clock Gating Control
This bit controls the clock gating for Port C. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port B Clock Gating Control
This bit controls the clock gating for Port B. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
Port A Clock Gating Control
This bit controls the clock gating for Port A. If set, the module receives
a clock and functions. Otherwise, the module is unclocked and disabled.
If the module is unclocked, a read or write to the module generates a
bus fault.
July 24, 2012
251
Texas Instruments-Production Data