LM3S6C11 Datasheet, PDF (451/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6C11 Microcontroller
Timer A Interval Load (GPTMTAILR) register (see page 479). Table 10-7 on page 451 shows the
values that are loaded into the timer registers when the timer is enabled.
Table 10-7. Counter Values When the Timer is Enabled in RTC Mode
Register
TnR
TnV
Count Down Mode
Not available
Not available
Count Up Mode
0x1
0x1
The input clock on a CCP input is required to be 32.768 KHz in RTC mode. The clock signal is then
divided down to a 1-Hz rate and is passed along to the input of the counter.
When software writes the TAEN bit in the GPTMCTL register, the counter starts counting up from
its preloaded value of 0x1. When the current count value matches the preloaded value in the
GPTMTAMATCHR register, the GPTM asserts the RTCRIS bit in GPTMRIS and continues counting
until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When the timer
value reaches the terminal count, the timer rolls over and continues counting up from 0x0. If the
RTC interrupt is enabled in GPTMIMR, the GPTM also sets the RTCMIS bit in GPTMMIS and
generates a controller interrupt. The status flags are cleared by writing the RTCCINT bit in GPTMICR.
In this mode, the GPTMTnR and GPTMTnV registers always have the same value.
In addition to generating interrupts, a μDMA trigger can be generated. The μDMA trigger is enabled
by configuring and enabling the appropriate μDMA channel. See “Channel Configuration” on page 336.
If the TASTALL bit in the GPTMCTL register is set, the timer does not freeze when the processor
is halted by the debugger if the RTCEN bit is set in GPTMCTL.
10.3.2.3
Input Edge-Count Mode
Note:
For rising-edge detection, the input signal must be High for at least two system clock periods
following the rising edge. Similarly, for falling-edge detection, the input signal must be Low
for at least two system clock periods following the falling edge. Based on this criteria, the
maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Count mode, the timer is configured as a 24-bit down-counter including the optional prescaler
with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the
lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three types of
events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of
the GPTMTnMR register must be cleared. The type of edge that the timer counts is determined by
the TnEVENT fields of the GPTMCTL register. During initialization, the GPTMTnMATCHR and
GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR
and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the
number of edge events that must be counted. Table 10-8 on page 451 shows the values that are
loaded into the timer registers when the timer is enabled.
Table 10-8. Counter Values When the Timer is Enabled in Input Edge-Count Mode
Register
TnR
TnV
Count Down Mode
GPTMTnILR
GPTMTnILR
Count Up Mode
Not available
Not available
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled
for event capture. Each input event on the CCP pin decrements the counter by 1 until the event
count matches GPTMTnMATCHR and GPTMTnPMR. When the counts match, the GPTM asserts
the CnMRIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared
July 24, 2012
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