LM3S6C11 Datasheet, PDF (174/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

System Control
OBSOLETE: TI has discontinued production of this device.
5.2.3
5.2.3.1
5.2.3.2
clock domain, register accesses must have a time delay between them. The watchdog timer can
be configured to generate an interrupt to the microcontroller on its first time-out and to generate a
reset on its second time-out.
After the watchdog's first time-out event, the 32-bit watchdog counter is reloaded with the value of
the Watchdog Timer Load (WDTLOAD) register and resumes counting down from that value. If
the timer counts down to zero again before the first time-out interrupt is cleared, and the reset signal
has been enabled, the watchdog timer asserts its reset signal to the microcontroller. The watchdog
timer reset sequence is as follows:
1. The watchdog timer times out for the second time without being serviced.
2. An internal reset is asserted.
3. The internal reset is released and the microcontroller loads from memory the initial stack pointer,
the initial program counter, and the first instruction designated by the program counter, and
then begins execution.
For more information on the Watchdog Timer module, see “Watchdog Timers” on page 491.
The watchdog reset timing is shown in Figure 20-9 on page 780.
Non-Maskable Interrupt
The microcontroller has three sources of non-maskable interrupt (NMI):
■ The assertion of the NMI signal
■ A main oscillator verification error
■ The NMISET bit in the Interrupt Control and State (INTCTRL) register in the Cortex^™-M3 (see
page 121).
Software must check the cause of the interrupt in order to distinguish among the sources.
NMI Pin
The NMI signal is the alternate function for GPIO port pin PB7. The alternate function must be
enabled in the GPIO for the signal to be used as an interrupt, as described in “General-Purpose
Input/Outputs (GPIOs)” on page 392. Note that enabling the NMI alternate function requires the use
of the GPIO lock and commit function just like the GPIO port pins associated with JTAG/SWD
functionality, see page 427. The active sense of the NMI signal is High; asserting the enabled NMI
signal above V_IH initiates the NMI interrupt sequence.
Main Oscillator Verification Failure
The LM3S6C11 microcontroller provides a main oscillator verification circuit that generates an error
condition if the oscillator is running too fast or too slow. If the main oscillator verification circuit is
enabled and a failure occurs, a power-on reset is generated and control is transferred to the NMI
handler. The NMI handler is used to address the main oscillator verification failure because the
necessary code can be removed from the general reset handler, speeding up reset processing. The
detection circuit is enabled by setting the CVAL bit in the Main Oscillator Control (MOSCCTL)
register. The main oscillator verification error is indicated in the main oscillator fail status (MOSCFAIL)
bit in the Reset Cause (RESC) register. The main oscillator verification circuit action is described
in more detail in “Main Oscillator Verification Circuit” on page 182.
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July 24, 2012
Texas Instruments-Production Data