LM3S6C11 Datasheet, PDF (23/828 Pages) Texas Instruments – Stellaris® LM3S6C11 Microcontroller

OBSOLETE: TI has discontinued production of this device.
Stellaris^® LM3S6C11 Microcontroller
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UART LIN Snap Shot (UARTLSS), offset 0x094 ............................................................... 565
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 566
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 567
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 568
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 569
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 570
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 571
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 572
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 573
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 574
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 575
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 576
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 577
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 578
Synchronous Serial Interface (SSI) ............................................................................................ 579
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 594
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 596
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 598
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 599
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 601
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 602
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 603
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 605
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 607
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 608
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 609
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 610
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 611
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 612
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 613
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 614
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 615
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 616
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 617
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 618
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 619
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 620
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 621
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 638
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 639
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 644
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 645
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 646
Register 6: I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 647
Register 7: I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 648
Register 8: I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 649
Register 9: I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 650
July 24, 2012
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