CC2510FX Datasheet, PDF (222/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

C2510Fx / CC2511Fx
0xDF16: BSCFG – Bit Synchronization Configuration
Bit Field Name
Reset R/W Description
7:6 BS_PRE_KI[1:0] 01
5:4 BS_PRE_KP[1:0] 10
3 BS_POST_KI
1
2 BS_POST_KP
1
1:0 BS_LIMIT[1:0]
00
R/W The clock recovery feedback loop integral gain to be used before a sync word
is detected (used to correct offsets in data rate):
R/W
00 K_I
01 2K_I
10 3K_I
11 4K_I
The clock recovery feedback loop proportional gain to be used before a sync
word is detected
R/W
00 K_P
01 2K_P
10 3K_P
11 4K_P
The clock recovery feedback loop integral gain to be used after a sync word is
detected.
0 Same as BS_PRE_KI
1 K_I /2
R/W The clock recovery feedback loop proportional gain to be used after a sync
word is detected.
0 Same as BS_PRE_KP
1 K_P
R/W The saturation point for the data rate offset compensation algorithm:
00 ±0 (No data rate offset compensation performed)
01 ±3.125% data rate offset
10 ±6.25% data rate offset
11 ±12.5% data rate offset
SWRS055D
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