CC2510FX Datasheet, PDF (108/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

C2510Fx / CC2511Fx
13.5.8 DMA Registers
This section describes the SFRs associated with the DMA Controller.
DMAARM (0xD6) – DMA Channel Arm
Bit Name
7
ABORT
6:5
4
DMAARM4
3
DMAARM3
2
DMAARM2
1
DMAARM1
0
DMAARM0
Reset
0
R/W
R0/W
-
R0
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
DMA abort. Ongoing DMA transfer or armed DMA channels
will be aborted when writing a 1 to this bit, and at the same
time select which DMA channels to abort by setting the
corresponding, DMAARM.DMAARMn bits to 1
0 Normal operation
1 Abort channels all selected channels
Not used
DMA arm channel 4
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 3
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 2
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 1
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
DMA arm channel 0
This bit must be set to 1 in order for any DMA transfers to
occur on the channel. For non-repetitive transfer modes, the
bit is automatically cleared when the transfer count is reached
SWRS055D
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