CC2510FX Datasheet, PDF (109/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

C2510Fx / CC2511Fx
DMAREQ (0xD7) – DMA Channel Start Request and Status
Bit Name
7:5
4
DMAREQ4
3
DMAREQ3
2
DMAREQ2
1
DMAREQ1
0
DMAREQ0
Reset
-
0
R/W
R0
R/W1
H0
0
R/W1
H0
0
R/W1
H0
0
R/W1
H0
0
R/W1
H0
Description
Not used
DMA transfer request, channel 4 (manual trigger)
Setting this bit to 1 will have the same effect as a single trigger
event.
This bit is cleared when the DMA channel is granted access.
DMA transfer request, channel 3 (manual trigger)
Setting this bit to 1 will have the same effect as a single trigger
event.
This bit is cleared when the DMA channel is granted access.
DMA transfer request, channel 2 (manual trigger)
Setting this bit to 1 will have the same effect as a single trigger
event.
This bit is cleared when the DMA channel is granted access.
DMA transfer request, channel 1 (manual trigger)
Setting this bit to 1 will have the same effect as a single trigger
event.
This bit is cleared when the DMA channel is granted access.
DMA transfer request, channel 0 (manual trigger)
Setting this bit to 1 will have the same effect as a single trigger
event.
This bit is cleared when the DMA channel is granted access.
DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte
Bit Name
7:0 DMA0CFG[15:8]
Reset
0x00
R/W
R/W
Description
The DMA channel 0 configuration address, high byte
DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte
Bit Name
7:0 DMA0CFG[7:0]
Reset
0x00
R/W
R/W
Description
The DMA channel 0 configuration address, low byte
DMA1CFGH (0xD3) – DMA Channel 1-4 Configuration Address High Byte
Bit Name
7:0 DMA1CFG[15:8]
Reset R/W
0x00 R/W
Description
The DMA channel 1 - 4 configuration address, high byte
DMA1CFGL (0xD2) – DMA Channel 1-4 Configuration Address Low Byte
Bit Name
7:0 DMA1CFG[7:0]
Reset
0x00
R/W
R/W
Description
The DMA channel 1 - 4 configuration address, low byte
SWRS055D
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