CC2510FX Datasheet, PDF (176/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

(if enabled) to signal that a new data packet
has
been
received.
The
USBCSOL.FIFO_FULL bit will be set when
there are two data packets in the OUT FIFO.
The AutoClear feature is supported for OUT
endpoints.
When
enabled,
the
USBCSOL.OUTPKT_RDY bit is cleared
automatically when USBMAXO bytes have been
read from the OUT FIFO. The AutoClear
feature is enabled by setting
USBCSOH.AUTOCLEAR=1. The AutoClear
feature can be used to reduce the time the
data packet occupies the OUT FIFO buffer and
is typically used for bulk endpoints.
A complementary AutoSet feature is supported
for IN endpoints. When enabled, the
USBCSIL.INPKT_RDY bit is set automatically
when USBMAXI bytes have been written to the
IN FIFO. The AutoSet feature is enabled by
setting USBCSIH.AUTOSET=1. The AutoSet
feature can reduce the overall time it takes to
send a data packet and is typically used for
bulk endpoints.
13.16.6.4 Endpoint 1 – 5 Interrupts
The following events may generate an IN EPx
interrupt request (x indicates the endpoint
number):
• A data packet that was loaded into the
IN FIFO has been sent to the USB host
(USBCSIL.INPKT_RDY should be set to
1 when a new packet is ready to be
transferred. This bit will be cleared by
HW when the data packet has been
sent)
• A STALL has been sent
(USBCSIL.SENT_STALL=1).
Only
Bulk/Interrupt endpoints can be stalled
• The IN FIFO is flushed due to the
USBCSIH.FLUSH_PACKET bit being set
to 1
Any of these events will cause
USBIIF.INEPxIF to be asserted regardless
of the status of the IN EPx interrupt mask bit
USBIIE.INEPxIE. If the IN EPx interrupt
mask bit is set to 1, the CPU interrupt flag
IRCON2.USBIF will also be asserted. An
interrupt request is only generated if
IEN2.USBIE and USBIIE.INEPxIE are both
set to 1. The x in the register names refer to
the endpoint number 1 - 5)
The following events may generate an OUT
EPx interrupt request:
C2510Fx / CC2511Fx
• A data packet has been received
(USBCSOL.OUTPKT_RDY=1)
• A STALL has been sent
(USBCSIL.SENT_STALL=1).
Only
Bulk/Interrupt endpoints can be stalled
Any of these events will cause
USBOIF.OUTEPxIF to be asserted
regardless of the status of the OUT EPx
interrupt mask bit USBOIE.OUTEPxIE. If the
OUT EPx interrupt mask bit is set to 1, the
CPU interrupt flag IRCON2.USBIF will also be
asserted. An interrupt request is only
generated
if
IEN2.USBIE
and
USBOIE.OUTEPxIE are both set to 1.
13.16.6.5 Bulk/Interrupt IN Endpoint
Interrupt IN transfers occur at regular intervals
while bulk IN transfers utilize available
bandwidth not allocated to isochronous,
interrupt, or control transfers.
Interrupt IN endpoints may set the
USBCSIH.FORCE_DATA_TOG bit. When this bit
is set the data toggle bit is continuously
toggled regardless of whether an ACK was
received or not. This feature is typically used
by interrupt IN endpoints that are used to
communicate rate feedback for Isochronous
endpoints.
A Bulk/Interrupt IN endpoint can be stalled by
setting the USBCSIL.SEND_STALL bit to 1.
When the endpoint is stalled, the USB
controller will respond with a STALL
handshake to IN tokens. The
USBCSIL.SENT_STALL bit will then be set
and an interrupt will be generated, if enabled.
A bulk transfer longer than the maximum
packet size is performed by splitting the
transfer into a number of data packets of
maximum size followed by a smaller data
packet containing the remaining bytes. If the
transfer length is a multiple of the maximum
packet size, a zero length data packet is sent
last. This means that a packet with a size less
than the maximum packet size denotes the
end of the transfer. The AutoSet feature can
be useful in this case, since many data
packets will be of maximum size.
13.16.6.6 Isochronous IN Endpoint
An Isochronous IN endpoint is used to transfer
periodic data from the USB controller to the
host (one data packet every USB frame).
If there is no data packet loaded in the IN FIFO
when the USB host requests data, the USB
SWRS055D
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