CC2510FX Datasheet, PDF (118/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

C2510Fx / CC2511Fx
Sample Rate
T1CC0H T1CC0L
8 kHz @ 24 MHz 0x0B
0xB7
8 kHz @ 26 MHz 0x0C
0xB1
16 kHz @ 24 MHz 0x05
0xDB
16 kHz @ 26 MHz 0x06
0x59
48 kHz @ 24 MHz 0x01
0xF3
48 kHz @ 26 MHz 0x02
0x1D
64 kHz @ 24 MHz 0x01
0x76
64 kHz @ 26 MHz 0x01
0x96
Table 53: Channel 0 Period Setting for some Sampling Rates (CLKCON.TICKSPD=000)
Since the DSM starts immediately after DSM
mode has been enabled by setting
T1CCTL1.CMP=111, all configuration should
have been performed prior to enabling DSM
mode. Also, the Timer 1 counter should be
cleared and started just before starting the
DSM operation (all write accesses to the
T1CNTL register will reset the 16-bit counter
while writing a value other than 00 to
T1CTL.MODE will start the counter). A simple
procedure for setting up DSM mode should
then be as follows:
1. Suspend timer 1 (T1CTL.MODE=00)
2. Clear timer counter by writing any
value to T1CNTL, (CNT=0x0000)
3. Set the sample rate by writing to
T1CC0.
4. Set Timer 1 channel 0 compare mode
(T1CCTL0.MODE=1)
5. Load first sample if available (or zero if
no sample available) into
T1CC1H:T1CC1L.
6. Set timer operation to modulo mode
(T1CTL.MODE=10)
7. Configure the DSM by setting the
MODE and CAP fields of the T1CCTL1
register.
8. Enable
DSM
(T1CCTL1.CMP=111)
mode
On each Timer 1 IRQ or Timer 1 DMA trigger,
write a new sample to the T1CC1H:T1CC1L
registers. The least significant bits must be
written to T1CC1L before the most significant
bits are written to T1CC1H.
The samples written must be signed 2’s
complement values. The 2 least significant bits
will always be treated as 0, thus the effective
sample size is 14 bits.
13.6.9 Timer 1 Registers
This section describes the following Timer 1
registers:
• T1CNTH – Timer 1 Counter High
• T1CNTL – Timer 1 Counter Low
• T1CTL – Timer 1 Control and Status
• T1CCTLn – Timer 1 Channel n
Capture/Compare Control
• T1CCnH – Timer 1 Channel n
Capture/Compare Value High
• T1CCnL Timer 1 Channel n
Capture/Compare Value Low
The TIMIF register is described in Section
13.9.7.
SWRS055D
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