CC2510FX Datasheet, PDF (185/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

C2510Fx / CC2511Fx
0xDE14: USBCSOL – OUT EP{1-5} Control and Status Low
Bit Field Name
Reset R/W Description
7 CLR_DATA_TOG 0
6 SENT_STALL
0
5 SEND_STALL
0
4 FLUSH_PACKET 0
3 DATA_ERROR
0
2 OVERRUN
0
1 FIFO_FULL
0
0 OUTPKT_RDY
0
R/W
H0
R/W
R/W
R/W
H0
R
R/W
R
R/W
Setting this bit will reset the data toggle to 0. Thus, setting this bit will force the
next data packet to be a DATA0 packet. This bit is automatically cleared.
This bit is set when a STALL handshake has been sent. An interrupt request
(OUT EP{1 - 5}) will be generated if the interrupt is enabled. This bit must be
cleared from firmware
Set this bit to 1 to make the USB controller reply with a STALL handshake
when receiving OUT tokens. Firmware must clear this bit to end the STALL
condition. It is not possible to stall an isochronous endpoint, thus this bit will
only have effect if the IN endpoint is configured as bulk/interrupt.
Set to 1 to flush next packet that is to be read from the OUT FIFO. The
OUTPKT_RDY bit in this register will be cleared. If there are two packets in the
OUT FIFO due to double buffering, this bit must be set twice to completely flush
the OUT FIFO. This bit is automatically cleared.
This bit is set if there is a CRC or bit-stuff error in the packet received. Cleared
when OUTPKT_RDY is cleared. This bit will only be valid if the OUT endpoint is
isochronous.
This bit is set when an OUT packet cannot be loaded into the OUT FIFO.
Firmware should clear this bit. This bit is only valid in isochronous mode
This bit is asserted when no more packets can be loaded into the OUT FIFO
full.
This bit is set when a packet has been received and is ready to be read from
OUT FIFO. An interrupt request (OUT EP{1 - 5}) will be generated if the
interrupt is enabled. This bit should be cleared when the packet has been
unloaded from the FIFO.
0xDE15: USBCSOH – OUT EP{1-5} Control and Status High
Bit Field Name
Reset R/W Description
7 AUTOCLEAR
0
6 ISO
0
5:4
00
3:1
-
0 OUT_DBL_BUF 0
R/W When this bit is set to 1, the USBCSOL.OUTPKT_RDY bit is automatically
cleared when a data packet of maximum size (specified by USBMAXO) has been
unloaded to the OUT FIFO.
R/W Selects OUT endpoint type
0 Bulk/Interrupt
1 Isochronous
R/W Reserved. Always write 00
R0 Not used
R/W Double buffering enable (OUT FIFO)
0 Double buffering disabled
1 Double buffering enabled
SWRS055D
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