CC2510FX Datasheet, PDF (175/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

C2510Fx / CC2511Fx
0
USBMAXI - 1
IN FIFO
USBMAX0 - 1
0
OUT FIFO
a)
0
USBMAXI - 1
USBMAX0 - 1
0
0
USBMAXI - 1
USBMAX0 - 1
0
IN FIFO
(Buffer 1)
OUT FIFO
(Buffer 2)
IN FIFO
(Buffer 2)
OUT FIFO
(Buffer 1)
b)
Figure 43: IN/OUT FIFOs, a) Single Buffering b) Double Buffering
13.16.6.2 Double Buffering
To enable faster transfer and reduce the need
for retransmissions, CC2511Fx implements
double buffering, allowing two packets to be
buffered in the FIFO in each direction. This is
highly recommended for isochronous
endpoints, which are expected to transfer one
data packet every USB frame without any
retransmission. For isochronous endpoint one
data packet will be sent/received every USB
frame. However, the data packet may be
sent/received at any time during the USB
frame period and there is a chance that two
data packets may be sent/received at a few
micro seconds interval. For isochronous
endpoints, an incoming packet will be lost if
there is no buffer available and a zero length
data packet will be sent if there is no data
packet ready for transmission when the USB
host requests data. Double buffering is not as
critical for bulk and interrupt endpoints as it is
for isochronous endpoint since packets will not
be lost. Double buffering, however, may
improve the effective data rate for bulk
endpoints.
To enable double buffering for an IN endpoint,
USBCSIH.IN_DBL_BUF must be set to 1. To
enable double buffering for an OUT endpoint,
set USBCSOH.OUT_DBL_BUF to 1.
13.16.6.3 FIFO Access
The endpoint FIFOs are accessed by reading
and writing to the registers in Table 36 on
Page 51. Writing to a register causes the byte
written to be inserted into the IN FIFO.
Reading a register causes the next byte in the
OUT FIFO to be extracted and the value of this
byte to be returned.
When a data packet has been written to an IN
FIFO, the USBCSIL.INPKT_RDY bit must be
set to 1. If double buffering is enabled, the
USBCSIL.INPKT_RDY bit will be cleared
immediately after it has been written and
another data packet can be loaded. This will
not generate an IN endpoint interrupt, since an
interrupt is only generated when a packet has
been sent. When double buffering is used
firmware should check the status of the
USBCSIL.PKT_PRESENT bit before writing to
the IN FIFO. If this bit is 0, two data packets
can be written. Double buffered isochronous
endpoints should only need to load two
packets the first time the IN FIFO is loaded.
After that, one packet is loaded for every USB
frame. To send a zero length data packet,
USBCSIL.INPKT_RDY should be set to 1
without loading a data packet into the IN FIFO.
A data packet can be read from the OUT FIFO
when the USBCSOL.OUTPKT_RDY bit is 1. An
interrupt will be generated when this occurs, if
enabled. The size of the data packet is kept in
the USBCNTH:USBCNTL registers. Note that
this value is only valid when
USBCSOL.OUTPKT_RDY=1. When the data
packet has been read from the OUT FIFO, the
USBCSOL.OUTPKT_RDY bit must be cleared. If
double buffering is enabled there may be two
data packets in the FIFO. If another data
packet
is
ready
when
the
USBCSOL.OUTPKT_RDY bit is cleared the
USBCSOL.OUTPKT_RDY bit will be asserted
immediately and an interrupt will be generated
SWRS055D
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