CC2510FX Datasheet, PDF(116/244 Page) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

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CC2510FX Datasheet, PDF (116/244 Pages) List of Unclassifed Manufacturers – True System-on-Chip with Low Power RF Transceiver and 8051 MCU

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C2510Fx / CC2511Fx

T1CC0

T1CCn

0x0000

0: Set output on compare

1: Clear output on compare

2: Toggle output on compare

3: Set output on compare-up,

clear on compare down

4: Clear output on compare-up,

set on compare-down

5: Set when T1CCn,

clear when T1CC0

6: Clear when T1CCn,

set when T1CC0

T1CCn T1CC0 T1CCn

T1CCn T1CC0 T1CCn

Figure 33: Output Modes, Timer Up/Down Mode

13.6.6 Timer 1 Interrupts

There is one interrupt vector assigned to the

timer. This is T1 (Interrupt #9, see

Table

39). The following timer events may generate

an interrupt request:

â¢ Counter reaches terminal count value

(overflow) or turns around on zero

â¢ Input capture event

â¢ Output compare event

The register bits T1CTL.OVFIF,

T1CTL.CH0IF,

T1CTL.CH1IF,

and

T1CTL.CH2IF contains the interrupt flags for

the terminal count value event (overflow), and

the three channel compare/capture events,

respectively. These flags will be asserted

regardless off the channel n interrupt mask bit

(T1CCTLn.IM). The CPU interrupt flag,

SWRS055D

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